1. Field of the Invention
The present invention relates to a semiconductor memory device including a memory having volatile and nonvolatile capabilities.
2. Description of the Related Art
Conventional Non-Volatile Dynamic Random Access Memory devices (hereinafter referred to as "NVDRAM") may be categorized into two types. One type is a NVDRAM in which a Dynamic Random Access Memory (hereinafter referred to as "DRAM") and an Electrically Erasable Programmable Read-Only Memory (hereinafter referred to as "EEPROM") are used in combination. The DRAM is a volatile semiconductor memory device and the EEPROM is a non-volatile semiconductor memory device. The other type is a NVDRAM in which a memory cell includes a ferroelectric material and functions both as a volatile memory and as a non-volatile memory.
A detailed description of the combination type NVDRAM can be found in "A 256 K-bit Non-Volatile PSRAM with Page Recall and Chip Store", 1991 Sym. VLSI Circuit Dig. Tech. papers, May, pp. 91-92, and in "Development of 256 K bit Non-Volatile DRAM (NV-DRAM) Operating as a Pseudo-SRAM", Sharp Technical Journal. No.49, pp.45-49, June, 1991. This type of NVDRAM has a DRAM and an EEPROM within the same memory cell structure (hereinafter, this type of memory cell will be referred to as a combination memory cell). The equivalent circuit of the combination memory cell is shown in FIG. 18.
In a normal DRAM-mode (or a pseudo-SRAM mode), the combination memory cell performs as a conventional DRAM cell which has a select transistor (SG) with storage capacitor (C1). In a store mode, immediately before the NVDRAM is turned off or at any time desired, all DRAM data is transferred to the EEPROM in all memory cells. In recall mode, the data stored in the non-volatile state is transferred from the EEPROM to the DRAM, where it can be accessed.
As a result, a high-speed access to the data stored in the volatile state in the DRAM can be realized during in the normal DRAM mode, while the data stored in the non-volatile state in the EEPROM is retained safely without supplying power to the NVDRAM following the store operation. The advantages of the combination type NVDRAM are that the data can be stored separately in the DRAM and in the EEPROM and there is no limitation as to the number of times the recall operation can be repeated.
On the other hand, a ferroelectric type NVDRAM is described in the following articles: (1) "An Experimental 512 K-bit Non-Volatile Memory with Ferroelectric Storage Cell" IEEE Journal of Solid State Circuits, vol. 23, pp. 1171-1175, October, 1988; (2) "A Ferroelectric DRAM cell for High-Density NVRAM's", IEEE Electron Device Lett., vol. 11, pp. 454-456, October, 1990; and (3) Japanese Laid-Open Patent Application No. 4-42498, "A Semiconductor Memory Device, and a Method for Read/Write the Semiconductor Memory Device".
Article (1) describes a ferroelectric type NVDRAM as including memory cells each having two transistors and two capacitors (hereinafter this type of NVDRAM will be referred to as a two-transistor/cell NVDRAM). In the two-transistor/cell NVDRAM, a read/write operation is performed in a recall/store mode which involves polarization reversal of the ferroelectric material included in the memory cells. However, the 2-transistor/cell NVDRAM cannot satisfy the required number of available polarization reversals (10.sup.15 to 10.sup.16 times) of the ferroelectric material in order to realize a practical memory device to be used based on 10 years with a cycle time of 100 nsec, because the possible number of the available polarization reversals of the ferroelectric material is limited to 10.sup.12 to 10.sup.13 times at maximum under the present situation.
Article (2) describes a ferroelectric DRAM cell in which polarization reversal only occurs during the non-volatile store/recall operation but not during the normal read/write operation. It is reported that ferroelectric fatigue does not pose a serious endurance problem for this DRAM cell.
Article (3) describes a semiconductor memory device having word lines selected by a row addresses and plate lines and sense amplifiers selected by column addresses to realize low power consumption and high-speed access operation.
The above mentioned ferroelectric type NVDRAMs use memory cells each incorporating a capacitor element which has a thin film made of a ferroelectric material with a crystal structure of a perovskite type, e.g. Y1 (a newly developed ferroelectric ceramic which is less fatigued by a rewrite operation; the composition thereof is yet to be published), PZT (PbZrTiO.sub.3, or lead zirconate titanate), PLZT (PbLaZrTiO.sub.3), PbTiO.sub.3, etc. Many kinds of ferroelectric material have been developed in order to realize an ideal ferroelectric thin film which has a large remanent polarization and a large dielectric constant and which is not fatigued.
When an AC voltage is applied to the capacitor element having the ferroelectric material, the polarization of the ferroelectric material shows a hysteresis characteristic as shown in FIG. 19. As seen from FIG. 19, the polarization state of the ferroelectric material, which is at point A when it is not polarized, shifts to point B when a positive electric field is applied to the ferroelectric material. The polarization state of the ferroelectric material returns only to point C (instead of A) when the electric field is removed, thus resulting in a positive remanent polarization. This remanent polarization vanishes when a negative electric field is applied. By further increasing the intensity of the negative electric field, the polarization of the ferroelectric material is reversed so that the polarization state shifts to point D. The polarization state of the ferroelectric material returns only to point E when the electric field is again removed, thus resulting in a negative remanent polarization.
Thus, by allowing the polarization of the ferroelectric material to be reversed so as to achieve positive or negative remanent polarization, given data can be stored in a non-volatile manner. Moreover, by simply applying or removing a positive or negative electric field, it can be ensured that the polarization state of the ferroelectric material of the above-mentioned capacitor element shifts only between points B and C or between points D and E, instead of having polarization reversals. Thus, given data can be stored in a volatile manner, as in the case of a usual DRAM. However, in order to retain the data thus stored in a volatile manner, refresh operations are required as in the case of a DRAM.
A ferroelectric type NVDRAM has the advantage that, since the memory cells thereof can be constituted by a smaller number of elements than in the case of a combination type NVDRAM, the cell areas can be reduced, thereby providing for further integration of the device.
Hereinafter, the structure and operation of an exemplary ferroelectric type NVDRAM, where two-transistor/cell memory cells are used, will be described. The two transistor/cell memory cell is known to be immune to possible variations in the fabrication process.
As shown in FIG. 20, this ferroelectric type NVDRAM includes a plurality of word lines WL and corresponding plate lines PT. The word lines WL are connected to a word line decoder 31. The plate lines PT are connected to a plate line decoder 32. The NVDRAM also includes a plurality of pairs of bit lines bit and bit-bar. Each pair of bit lines bit and bit-bar are connected to a sense amplifier 33. In FIG. 20, only one pair of bit lines bit and bit-bar and their corresponding sense amplifier 33 are shown.
A memory cell 34 is provided in each portion where one of the word lines WL and its corresponding plate line PT intersect a pair of bit lines bit and bit-bar. In FIG. 20, only one memory cell 34 is shown. The memory cell 34 includes two capacitor elements C.sub.1 and C.sub.2 and two selection transistors Q.sub.1 and Q.sub.2. One of the terminals of the capacitor element C.sub.1 is connected to the bit line bit via the transistor Q.sub.1. One of the terminals of the capacitor element C.sub.2 is connected to the bit line bit-bar via the transistor Q.sub.2. The other terminals of the capacitor elements C.sub.1 and C.sub.2 are connected to the plate line PT. Gates of the transistors Q.sub.1 and Q.sub.2 are connected to the word line WL.
The above-described ferroelectric type NVDRAM operates in the following manner. The word line decoder 31 and the plate line decoder 32 select, respectively, one of the word lines WL and one of the plate lines PT, in accordance with an address signal input to an address buffer 35. Then, the memory cell 34 is accessed in a mode chosen in accordance with a control signal input to a control signal input buffer 36. Specifically, the access operation is conducted in one of the following modes: in a DRAM mode (or a volatile mode) for accessing data stored in a volatile state, the NVDRAM is controlled by a DRAM mode timing control circuit 37; in a recall mode for reading and rewriting data stored in a non-volatile state, the NVDRAM is controlled by a recall mode timing control circuit 38; in a store mode for writing data stored in a non-volatile state, the NVDRAM is controlled by a store mode timing control circuit 39. The inputting and the outputting of the data to be accessed are conducted through a data I/O interface 40.
Hereinafter, a write operation in the store-mode, controlled by the store-mode timing control circuit 39, will be described with reference to FIGS. 21 and 22.
As shown in FIG. 21, when data "0" is to be written, for example, a voltage of 0 V and a voltage of 5 V (e.g. supply voltage Vcc) are applied to, respectively, the bit line bit and the bit line bit-bar, and a voltage pulse which varies from 0 V to 5 V and back to 0 V is applied to the plate line PT while keeping the word line WL in an active state. As a result, the polarization state of the ferroelectric material of the capacitor element C.sub.1 shifts from point C or point E to point B, and then to point C as shown in FIG. 19. The polarization state of the ferroelectric material of the capacitor element C.sub.2 shifts from point D to point E and back to point D as shown in FIG. 19. Accordingly, after these voltages are stopped being applied, the ferroelectric materials of the capacitor elements C.sub.1 and C.sub.2 have the remanent polarizations of points C and E, respectively, so that the data "0" is stored in a nonvolatile manner.
When data "1" is to be written, as shown in FIG. 22, a voltage of 5 V (e.g. supply voltage Vcc) and a voltage of 0 V are applied to, respectively, the bit line bit and the bit line bit-bar, in contrast to the voltages of 0 V and 5 V applied in the above-mentioned case of writing the data "0". A voltage pulse which varies from 0 V to 5 V and back to 0 V is applied to the plate line PT while keeping the word line WL in an active state, whereby the ferroelectric materials of the capacitor elements C.sub.1 and C.sub.2 are made to have the remanent polarizations of points E and C, respectively, so that the data "1" is stored in a non-volatile manner.
Next, a recall operation of data in the recall mode, controlled by the recall mode timing control circuit 38, will be described with reference to FIG. 23. In this operation, the pair of bit lines bit and bit-bar are precharged at a voltage of 0 V and thereafter are placed in an open state. Then, a voltage which varies from 0 V to 5 V is applied to the plate line PT while keeping the word line WL in an active state. As a result, in the case where data "0" is stored, the polarization state of the ferroelectric material of the capacitor element C.sub.1 shifts from point C to point B as shown in FIG. 19, while the polarization state of the ferroelectric material of the capacitor element C.sub.2 shifts from point E to point B. Thus, the polarization of the ferroelectric material of the capacitor element C.sub.2 is reversed, so that the potential of the bit line bit-bar, which is connected to the capacitor element C.sub.2, becomes higher than that of the bit line bit by hundreds of mV (millivolts).
Accordingly, by sensing the difference between the potentials of the bit lines bit and bit-bar by the sense amplifier 33, the data stored in a non-volatile manner can be read out. However, the polarization states of the capacitor elements C.sub.1 and C.sub.2 both shift to point B, so that the data which has been stored in a non-volatile manner is lost, resulting in a destructive read-out of the data.
In the recall-mode, the data which has been recalled can be rewritten in the NVDRAM by storing the data in a non-volatile manner. This can be conducted by, after the pair of bit lines bit and bit-bar are set at 0 V and 5 V by the sense amplifier 33, applying a voltage which varies from 0 V to 5 V and back to 0 V to the plate line PT in the same procedure as that for the store-mode. In addition, by maintaining the plate line PT at 0 V after the above procedure, the potentials set for the pair of bit lines bit and bit-bar can be stored in the memory cell 34 as charges, thus realizing storage in a DRAM mode (to be described later).
The potential difference in the pair of bit lines bit and bit-bar which is generated in the recall-mode is in proportion to the intensity of the remanent polarization and in inverse proportion to the bit line capacitance. Accordingly, a larger potential difference can be obtained as the remanent polarization increases and as the bit line capacity decreases, thereby facilitating the detection by the sense amplifier 33.
An access operation in the DRAM-mode, controlled by the DRAM-mode timing control circuit 37, is achieved by the same procedure as that for a conventional DRAM except that a voltage of 0 V or 5 V (e.g. supply voltage Vcc) is applied to the plate line PT. Thus, the polarization states of the ferroelectric materials of the capacitor element C.sub.1 and C.sub.2 shift only between point D and point E or between point B and point C, neither of which results in any polarization reversal. Therefore, the read and write of the data stored in a volatile manner can be conducted by utilizing the charges stored in the capacitor element C.sub.1 and C.sub.2 alone, as in the case of a conventional DRAM. Refresh operations are required to retain the data stored in the volatile matter in the DRAM mode.
Although a ferroelectric type NVDRAM using two transistor/cell memory cells, which is relatively immune to influences of the fluctuation in the thickness of the ferroelectric material thin film, was described above, substantially the same principle applies to an NVDRAM having a memory cell array structure of one transistor/cell type having relatively small cell areas and thus being suitable for higher degrees of integration, such as that disclosed in U.S. Pat. No. 5,381,379. In addition, the same principle may be applied to NVDRAMs in which addresses are multiplexed and a row address strobe signal RAS-bar and a column address strobe signal CAS-bar are used, as in a usual case of a DRAM. Multiplexing the addresses has the advantage of reducing the number of terminal pins for the addresses so as to obtain a higher integration of the device.
FIG. 24 shows a configuration of a conventional non-volatile semiconductor memory device 200 using NVDRAMs 41 as mentioned above. An address is applied to each NVDRAM 41 via an address bus from an external control circuit or a microprocessor unit (MPU). Data is input to and output from the NVDRAM 41 via a data bus. A voltage Vcc is also supplied and control signals such as a non-volatile enable signal NE-bar, a chip enable signal CE-bar, an output enable signal OE-bar, a write enable signal WE-bar, and a refresh signal RFSH-bar are input to respective terminals of the NVDRAM 41.
Operations in the device 200 are as follows. As shown in FIG. 25, a self-recall operation is performed for all of the NVDRAM 41 when the power is turned on and the data stored in each NVDRAM 41 is transferred from a non-volatile state into a volatile state (referred to as a power-on recall). The self-recall operation is performed by setting the non-volatile enable signal NE-bar at the low level and returning to the high level (i.e. giving a low-level pulse.), while the output enable signal OE-bar is alternately set at the low level and the high level (i.e. giving a plurality of low-level pulses repeatedly). And then normal operations of read/write/refresh are performed at high speed in the volatile DRAM mode. At the time just before the power is turned off or at any desired time, the store operation is performed for every NVDRAM 41 by giving a low-level pulse to the non-volatile enable signal NE-bar and then to the write enable signal WE-bar.
The self-recall operation, the self-store operation and the circuit structures for performing the operations suitable for use in connection with the present invention are shown in U.S. application Ser. No. 08/325,957, filed on Oct. 20, 1994 and entitled "A NON-VOLATILE DYNAMIC RANDOM ACCESS MEMORY", the disclosure of which is hereby incorporated by reference.
In a conventional NVDRAM used in a pseudo-SRAM mode, a refresh operation synchronized with an external control signal is referred to as an "auto-refresh operation", and a refresh operation may otherwise be referred to as a "self-refresh operation". Similarly, a recall/store operation synchronized with an external control signal may be referred to as an "auto-recall/store operation", and a recall/store operation may otherwise be referred to as a "self-recall/store operation". However, in the following explanation, the terms "self-store", "self-refresh" and "self-recall" include "auto-store", "auto-refresh" and "auto-recall", respectively.
It is possible to operate the combination type NVDRAM and the ferroelectric type NVDRAM described above in the store-mode for writing data in a non-volatile manner and in the recall-mode for reading the data stored in the non-volatile manner. However, in the case of the combination type NVDRAM, available times to rewrite the EEPROM are limited to about one hundred thousand times, so that the EEPROM will soon reach the end of its lifetime if frequent rewrite operations are conducted.
In the case of a ferroelectric type NVDRAM, the ferroelectric materials included in the capacitor elements C.sub.1 and C.sub.2 permit only a limited number of polarization reversal so that the recalling/store operations are limited to about 10.sup.8 to 10.sup.12 times. Therefore, the lifetime of the memory cells 34 can expire in a few days by conducting successive accessing at a cycle of about 10 MHz. Therefore, studies are being conducted on materials which leave a large remanent polarization and permit a large number of polarization reversals.
In view of the above problems, in the case of the combination type NVDRAM, the EEPROM is prevented from undergoing an excessively large number of rewrite operations by ensuring that only the DRAM is accessed during usual operations. Accordingly, the data stored in the DRAM is saved in the EEPROM only immediately before the NVDRAM device is turned off, and that all the data is recalled into the DRAM in a recall-mode when the NVDRAM device is turned on the next time.
In the case of a ferroelectric type NVDRAM, the number of the access operations that result in polarization reversals is minimized by ensuring that access operations in the DRAM-mode, which do not result in any polarization reversal, are conducted during usual read/write operations and that the data in the memory cells 34 is stored in a non-volatile manner only before the NVDRAM device is turned off. In the ferroelectric type NVDRAM device, all the data stored in the non-volatile state is recalled to the data stored in the volatile state in the first read operation when the NVDRAM device is turned on the next time. In addition, since the access operation in the recall/store mode requires varying a voltage level of the plate line PT, access operation in the DRAM mode has advantages of reducing a power consumption and realizing a high speed access operation.
The above-mentioned conventional NVDRAM devices perform the recall operation, the refresh operation, the read/write operation in a volatile mode, and refresh operations in accordance with a given combination of a plurality of external input control signals: a non-volatile enable signal NE-bar, a chip enable signal CE-bar, an output enable signal OE-bar, a write enable signal WE-bar and a refresh signal RFSH-bar. In a case of multiplexing addresses, a combination of a row address strobe signal RAS-bar, a column address strobe signal CAS-bar, an output enable signal OE-bar and a write enable signal WE-bar etc, is used.
For example, in a recall mode, the non-volatile enable signal NE-bar and the output enable signal OE-bar are set at the low level (or activated), and in a store mode, the non-volatile enable signal NE-bar and the write enable signal WE-bar are set at the low level. A read operation in a volatile mode is conducted by setting the chip enable signal CE-bar and the output enable signal OE-bar at the low level, and a write operation in a volatile mode is conducted by setting the chip enable signal CE-bar and the write enable signal WE-bar at the low level.
The refresh operation for the data stored in the volatile state can be automatically conducted by providing a self-refreshing system as in the case of a pseudo SRAM. In the self-refreshing system, the refresh operations are sequentially performed for the memory cells by automatically generating addresses by using an internal address counter based on a clock signal. Specifically, the self-refresh operation is conducted by setting a refresh signal RFSH-bar at the low level, or by setting the column address strobe signal CAS-bar at the low level before the row address strobe signal RAS-bar is set at the low level. This enables the simplification of the structure of the peripheral circuits and control of the refresh operations.
In such conventional NVDRAM devices, the data stored in the non-volatile state in every NVDRAM 41 is self-recalled and transferred into the volatile state when the power is turned on. Therefore, the refresh operations are required for retaining the data stored in the volatile state until the store operation is performed. The data never accessed is also self-recalled when the power is turned on (power-on recall operation) and is retained by refresh operations until the store operation is performed or just before the power is turned off (power-off store operation). This may increase a power consumption.
Furthermore, an increasing number of the NVDRAMs 41 operated in the volatile manner in the non-volatile semiconductor memory device result in an increasing power consumption for recall/store operations for a large number of the memory cells in the NVDRAMs 41. Specifically, the power-on recall operation and the power-off store operation require a large current supply in order to be performed in a short time for ensuring the security of the data.
The above-mentioned problems are common to both the case where the NVDRAM device is implemented as a monolithic memory device and the case where the memory cell is implemented as a memory module for a single chip microcomputer.
In addition, a conventional NVDRAM device requires an additional control signal (non-volatile enable signal NE-bar) as compared with a pseudo-SRAM or a normal SRAM. This results in a lack of compatibility with the control signals of existing IC cards which are standardized by the Personal Computer Memory Card International Association (PCMCIA) or the Japan Electronic Industry Development Association (JEIDA). Hereinafter, this type of standardized IC card will be referred to as a PC card.
In a case where a cache memory using an SRAM or a DRAM is provided to the conventional NVDRAM device, some of the above-mentioned problems may be resolved. However, this may bring on a new problem as follows:
A significant large capacity of cache memory is required to obtain a sufficient so-called "hitting ratio" which means a probability of performing a read/write operation without a recall operation. Transferring the data form the NVDRAM device to the cache memory having a large capacity requires a long time, for example, on the order of about 51.2 msec for transferring data of 512 K byte to a cache memory of 512 K byte (4 M bit) with 100 nsec cycle. In a case where the cache memory has 2 M byte (16 M bit), it takes about 200 msec.